Formal Verification Engineer/Researcher
2011 - present: Employed by Calypto Design Systems where I work on their sequential equivalence checking tool SLEC.
2007 - 2011: Employed by IBM to work on a formal verification tool (SixthSense) in Austin,
2004 - 2009: Earned my PhD from UC Berkeley.
I was advised by Robert Brayton and
studied Computer Aided Design. In 2009 I authored my PhD thesis describing advances in
sequential logic synthesis and formal verification.